Electrostatic Discharge (“ESD”) is a serious problem for CMOS semiconductor devices since it has the potential to destroy an entire device. Therefore, protection from ESD discharge has become an important issue in CMOS ICs. The advanced processes of sub-micron CMOS technologies greatly degrade the ESD protection strength of CMOS ICs. Circuit designers have concentrated their efforts on developing adequate protection mechanisms.
In general, an IC should be protected for ESD discharge between any pair of pins. A protection circuit should behave as an ideal switch in parallel with the nodes to be protected; such that when an ESD event occurs, it behaves as a shortcircuit while during normal operation of the IC, it remains in a high impedance state.
An existing option is to use an RC-controlled ESD clamp that would sink the ESD current by switching ‘on’ during the ESD event while remaining ‘off’ during normal operation. FIG. 1 illustrates an R-C controlled ESD clamp circuit according to the PRIOR ART. The ESD conduction path is provided from Rail11 to Rail12 through NMOS transistor N12. The gate of N12 is controlled by an inverter formed by PMOS transistor P11 and NMOS transistor N11. The inverter itself is driven by ESD-transient detection circuit formed by resistor R11 and capacitor C11.
Initially, the nodes VG and VX are floating because the IC is in the floating condition without power supplies. An ESD event on Rail11 with respect to Rail12 will very slowly charge capacitor C11 and slowly raise the voltage level of node VG. The RC time constant of the RC-circuit R11-C11 is kept higher than the rise time of ESD voltage pulse at Rail11. Thus the voltage level of VG is increased much slower than the voltage level on Rail11. Due to the delay of voltage increase on node VG, PMOS P11 is turned-on by the ESD voltage and conducts ESD voltage into the node VX to turn ‘on’ the ESD clamping NMOS transistor N12. The turned-on N12 provides a low impedance path between rails Rail11 and Rail12 that discharges the ESD current and clamps the ESD voltage across them.
The turn-on time of ESD-clamp N12 is kept at least equal to half the energy discharging time of the ESD event. The turn-on time of N12 can be adjusted by the RC time constant of the RC-circuit and the relative sizing of P11 and N11. Generally P11 is kept strong and N11 is kept relatively much weaker to ensure a faster response and longer duration turn-on of N12. The symbol used for the clamp is shown in FIG. 1.
IEEE paper “Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Sub micron CMOS VLSI” by Ming-Dou Ker provides a detailed description of such a circuit. This paper also describes a whole chip ESD protection design using such a clamp, in which the clamp is placed between VDD and VSS rails with Rail11 as VDD and Rail12 as VSS.
One limitation to this clamp is that it cannot be used to provide ESD conduction path from rails that are normally at lower voltage to rails that are at higher voltage. This means that in normal operation, Rail11 should always be at voltage higher than or equal to that at Rail12.
This is because if in normal operation we have Rail11 at lower voltage and Rail12 at higher voltage, node VX is pulled-down to the lower voltage through PMOS transistor P11. Thus voltage at node VX will always be one Vtp (PMOS transistor's threshold voltage) higher than the lower voltage, keeping N12 in its sub-threshold region. N12 is large enough to conduct significant amount of static current, even though operating in its sub-threshold region.
U.S. Pat. Nos. 5,946,177, 5,610,791, 6,104,588, 5,953,190 show existing methods of providing ESD conduction paths between VDD and VSS Rails:
FIG. 2(a) shows how an ESD discharge on the VDD rail with respect to VSS is conducted through RC-clamp C2a, while an ESD discharge on VSS rail with respect to VDD is conducted through diode D2a. This scheme is applicable to single supply ICs. As more circuits and functions are integrated into a single chip, a chip often has more than one power supply with different voltage levels. For example, chips have their internal core circuitry operating at one supply voltage level and interfacing I/O circuitry operating at different supply voltage. For such mixed-voltage ICs it becomes important to provide ESD conduction paths between separate supplies to have a robust whole chip ESD protection design.
FIG. 2(b) shows the conventional method to provide ESD conduction path between two separate supply rails. Here I/O supply voltage VDDO is assumed to be at higher supply voltage than core supply VDD. ESD conduction path from VDD rail to VDDO rail is provided through diode D21b and the conduction path from VDDO to VDD through diode chain D22b, D23b, D24b. This scheme requires the IC to be powered-up and powered-down sequentially because of the presence of diode D21b (refer application note “Power-Up Behavior of Pro-ASIC 500K Devices” by ACTEL). Also, diodes in series will degrade the ESD performance and will require larger area for low resistance ESD conduction path. Further, if the voltage difference between VDDO and VDD is large, more than one diode will be required in series. The diode chain will also cause problems during power-up and power-down of the IC. For large differences between VDDO and VDD supplies, an RC-clamp is sometimes used instead of a diode chain, as shown in FIG. 2(c). But this too does not overcome the power sequence requirement.
In some ICs, it is required to have separate isolated power supply and ground rails for different sections of the IC, to avoid noise coupling between ‘noisy’ and ‘quiet’ rails. For example power/ground rails of the analog section of an IC are kept isolated from power/ground rails of the digital section to prevent the noisy digital section from affecting the performance of the quiet analog section. Here too it becomes necessary to provide ESD conduction paths between the normally isolated supplies rails.
FIG. 3(a) shows another method to provide an ESD conduction path between two isolated power rails. Here the ESD conduction path between quiet analog section supply voltage VDDQ and noisy digital section supply VDD is provided through diodes D31a and D32a. However these diodes do not provide perfect isolation during normal operations. Any noise greater than the voltage threshold of the diodes will overcome the isolation barrier. Further, this scheme requires both supplies VDDQ and VDD to be powered-up and powered-down simultaneously.
To give a better isolation, a chain of diodes is used instead of a single diode, as shown in FIG. 3(b). However this degrades the ESD performance and requires a larger area for providing a low resistance ESD conduction path. This scheme also requires both supplies VDDQ and VDD to be powered-up and powered-down simultaneously.
A perfect isolation is provided in normal operation by using RC-clamps for ESD conduction, as shown in FIG. 3(c). One such similar scheme is described in U.S. Patent Application No. 2002/0085328 A1. However an RC-clamp uses a large area and therefore using two separate RC-clamps will require excessively large area.
The same problem occurs when this scheme is used for isolated ground rails, as shown in FIGS. 3(d), 3(e), 3(f).